Infosys
· Hyderabad, Telangana
·Posted 15 Aug 2026
Full-time
Hyderabad, Telangana
Responsible for Design and development of critical analog, mixed-signal, and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership
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